(1) Field of the Invention
The present invention relates to the manufacture of integrated circuits in general, and in particular, to a method of improving tungsten filling of via and contact holes through the use of partial and no resist in etching the holes.
(2) Description of the Related Art
Interconnecting devices in semiconductor substrates is posing more challenges as the miniaturization progresses from very large scale integration (VLSI) to ultra scale integration (ULSI), and, in fact, further down to feature sizes less than 0.18 micrometers (xcexcm). As certain feature sizes become smaller, the thickness of some of the insulators cannot be scaled down accordingly because of the needed electrical strength of the insulating material. Thus, as the diameter of the vertical vias (that connect the wiring layers in a substrate) and contact holes (which reach the semiconductor substrate and provide contact to the devices within the substrate), the thickness of the insulator that separates those levels cannot be reduced at the same rate, and hence the aspect ratio, that is, the ratio of depth to the diameter of the hole, becomes larger than before.
Consequently, it is becoming more and more difficult to fill high aspect ratio, deep holes fully, that is, without voids or, what is sometimes known as xe2x80x9ckey-holesxe2x80x9d, as described below. This is true even with tungsten, which is a preferred metal for filling via and contact holes because its deposition is very conformal and results in remarkably good filling of vertical walled hole openings of relatively low aspect ratio. Also, tungsten (W) is preferred because of its low resistivity and because it can be deposited at temperatures below 500xc2x0 C. by chemical vapor deposition (CVD) using the hydrogen or silane reduction of tungsten hexafluoride (WF6). As is known in the art, tungsten may be selectively CVD deposited into hole openings, or CVD blanket deposited as a layer and etched back to expose the metal studs or plugs in the holes. However, due to lateral encroachment and wormholes (see Wolf, S., and Tauber, R. N. xe2x80x9cSilicon Processing for the VLSI Era,xe2x80x9d vol. 2, Lattice Press, Sunset Beach, Calif., 1990, pp. 245-248), blanket CVD W and etch back has been more widely adopted for contact hole and vial filling. Although the tungsten layer can be patterned to provide lateral wiring lines, the preferred method is to pattern the layer to expose only the studs and wire these with traditional aluminum, or, more recently, copper interconnection metallurgy. The studs are referred to as W-plugs.
A prior art process for forming W-plug contacts on a silicon wafer (100) substrate is described in U.S. Pat. No. 5,554,565 by Liaw, et al., as shown in FIGS. 1a-1f. Referring first to FIG. 1a, there is shown a cross section of a portion of a self-aligned polysilicon gate MOSFET. Shown is implant (120) representing a source or drain and the polysilicon gate (130). The silicon oxide field isolation(FOX) (110) is also shown.
A layer of dielectric material is first deposited onto the silicon surface using low-pressure-chemical-vapor-deposition(LPCVD) or plasma-enhanced-chemical-vapor-deposition(PECVD). The layer is formed by the thermal decomposition of tetraethyl orthosilicate (TEOS) at temperatures below 650xc2x0 C. Doping of the layers with boron and phosphorous allows them to flow at low temperatures. In a typical application, a layer of undoped TEOS (140) is first deposited, forming silicon oxide. This is followed by a thicker layer of doped TEQS (150) which has the lower flowing temperature properties of BPSG. The initial undoped layer precludes any unwanted doping of the silicon by the BPSG.
As deposited, the surface of the BPSG layer replicates the non-planar surface of the silicon substrate. The wafer is annealed at 800 to 900xc2x0 C. causing the BPSG to flow, thereby planarizing its upper surface(FIG. 1b). The BPSG is then etched back by reactive-ion-etching (RIE) to reduce its thickness but maintaining the surface planarity as shown in FIG. 1c. Photoresist (160) is applied and the contact openings are patterned using standard photolithographic techniques. RIE is then used to form the vertical contact openings in the BPSG exposing the silicon active devices (FIG. 1d).
Although the flowing of the BPSG provides a smooth upper surface, its thickness is not necessarily exactly the same over all the contact areas of the chip. The thickness depends upon the topology of the surrounding area. Thus when the contact holes are subsequently opened by RIE, some over-etching will occur at contacts where the BPSG is thinner. Since the substrate diffusions are very shallow to begin with, any over-etching could jeopardize them. Additionally, because of device miniaturization, the area of the contact approaches that of the silicon active area. A slight misalignment of the contact mask could easily cause the contact opening to miss the device implant area resulting in shorted junctions.
For these reasons an implant is made through the contact openings to reinforce the active regions of the devices(represented by the arrows in FIG. 1d). The silicon in the exposed contact areas is implanted with the appropriate dopant to provide a concentration of 2xc3x971014 to 2xc3x9710xe2x80x25 dopant atoms/cm2. Some products may require only one type of contact. For example, in NMOS technology the (100) diffused contacts can be entirely of n-type. Here, the appropriate implant may be performed without masking. For complimentary MOS(CMOS) technology, where both n- and p-type contacts are required, a first implant of p-type dopant is directed at all contacts. Then the p-type contacts are covered with a photoresist block-out mask and the n-contacts are implanted with a higher dose of n-type dopant to over-compensate the previous p-type implant. Using this procedure eliminates the need for an additional photolithographic step to shield the n-contacts.
Under the conventional procedure, these contact implants are next activated by rapid-thermal-annealing(RTA). This causes the BPSG to flow at the upper edge (170) (FIG. 1e) and severely encroach into the contact opening if the anneal temperature is above 950xc2x0 C. A Ti/TiN barrier metallization (180) (FIG. 1f) is then deposited and a barrier annealing is performed between 550 and 700xc2x0 C. to secure a bond of the Ti to the silicon and to the BPSG. Finally a layer of CVD tungsten (190) is deposited to fill the contact opening. The encroachment of the BPSG into the contact opening causes a restriction to the filling of the contact hole by the tungsten (190) leaving a void, or, key-hole, (195) in the center. Depending upon the degree of the overhang and the size of the contact opening, the thin tungsten walls surrounding the void have the potential for subsequent electrical failure.
In order to alleviate this potential electrical failure, Liaw, et al., propose an improved method for the fabrication of an ohmic, low resistance contact to heavily doped silicon by using a CVD deposited tungsten plug provided with Ti/TiN barrier metallurgy. The method provides for surface planarization by depositing first a layer of silicon oxide followed by a layer of borophosphosilicate glass onto a silicon wafer containing integrated circuit devices. After the glass is thermally flowed to planarize its surface, it is etched back to a suitable thickness and a second layer of silicon oxide is deposited over the now-planar surface. Contact holes are patterned in the composite silicon oxide-glass-silicon oxide structure and the exposed silicon device contacts are ion-implanted. The implant is then activated by rapid-thermal-annealing. The presence of the second silicon oxide layer prevents the upper corners of the contact openings from flowing and encroaching into the opening as would occur in its absence. This provides for void-free filling of the contact openings by the tungsten contact deposition.
In another approach, Chen, et al., of U.S. Pat. No. 6,025,273 disclose a method for etching reliable small contact holes in an interlevel dielectric (ILD) layer with improved profiles for semiconductor integrated circuits using a carbon doped hard mask. The method increases the ILD etch rate while reducing residue build-up on the contact hole sidewall. This provides a process for making contact holes smaller than 0.25 xcexcm in width. After depositing the ILD layer over the partially completed integrated circuit which includes patterned doped first polysilicon layers, a second polysilicon layer is deposited and doped with carbon by ion implants-lion. A photoresist mask is used to etch openings in the carbon doped polysilicon layer to form a hard mask. The photoresist is removed, and the contact holes are plasma etched in the ILD layer while free carbon released from the hard mask, during etching, reduces the free oxygen in the plasma. This results in an enhanced fluorine etch rate for the contact holes in the ILD layer and reduces the residue build-up on the sidewalls of the contact holes. The hard mask is anneal in O2 to form an oxide layer and any surface carbon is removed in a wet etch. Reliable metal plugs is formed by depositing a barrier layer, such as titanium (Ti) or titanium nitride (TiN) and a metal such as tungsten (W) and etching back or chemical/mechanical polishing back to the oxide layer.
A poly mask approach is taught by Kuo, et al., in U.S. Pat. No. 5,563,098 to form buried contact holes. A layer of silicon oxide is provided overlying a semiconductor substrate. A layer of polysilicon is deposited overlying the silicon oxide layer. The polysilicon layer is covered with a layer of photoresist which is exposed and developed to provide a photoresist mask. The polysilicon layer is etched away where it is not covered by the photoresist mask wherein a polymer buildup is formed on the sidewalls of the polysilicon layer. Ions are implanted into the silicon oxide layer not covered by the photoresist mask. The photoresist mask is removed whereby the polymer buildup is also removed. Thereafter, the silicon oxide layer not covered by the polysilicon layer is etched away to complete the formation of the buried contact hole with reduced polymer buildup in the fabrication of an integrated circuit.
The present invention discloses a method of W-filling deep vias and contact holes without the commonly encountered void, or, key-hole, problem. This is accomplished by the etching of the via or contact hole with a judicious use of a partial resist and no resist during the etching of the hole opening.
It is therefore an object of the present invention to provide a method of improving tungsten-filling of a hole opening without the presence of voids or key-holes in order to improve the over-all reliability of metal vias and contacts in a semiconductor substrate.
It is another object of the present invention to provide a method of improving tungsten (W)-filling of a hole opening in a semiconductor substrate by using a hard dielectric anti-reflective coating (DARC) mask.
It is still another object of the present invention to provide a method of improving W-filling of a hole opening in a substrate by using a photoresist mask first, and then a hard mask comprising a DARC layer during the etching of the hole opening.
It is yet another object of the present invention to provide a method of improving W-filling of a hole opening in a substrate by using a first main-etch (ME) with a photoresist mask, and then a second ME with a hard mask during the etching of the hole opening.
It is still another object of the present invention to provide a faceted via/contact hole with tapered side-walls in order to form metal plugs without the presence of key-holes.
These objects are accomplished by providing a semiconductor substrate having a substructure of devices formed therein; forming an etch-stop liner over said substrate; forming an interlevel dielectric (ILD) layer over said etch-stop layer; forming a dielectric anti-reflective coating (DARC) layer over said ILD layer; forming a patterned resist-mask over said DARC layer; performing DARC etch through said resist-mask to form a DARC hard-mask; performing a first main-etch (ME) through said resist-mask to form a partial opening in said ILD layer; removing said resist-mask; performing a second ME through said DARC hard-mask to form a via/contact hole with a taper in said ILD layer until said etch-stop liner is reached at the bottom of said via/contact hole opening while at the same time said via/contact hole opening in said DARC layer is faceted; removing said etch-stop liner at the bottom of said hole opening until substrate surface is reached; forming metal plug in said hole opening; and removing any excess metal from the surface of said substrate.
These objects are further accomplished by providing a semiconductor substrate; a hole opening in said substrate; and said hole opening having a faceted entrance and tapered side-walls.